1. Field of the Invention
This invention relates to a semiconductor switching element and more particularly to a field controlled thyristor.
2. Description of the Prior Art
Up to now, various field controlled thyristors have been proposed which comprise a first emitter region having a first conductivity type, exposed to one main surface of a semiconductor substrate; a second emitter region having a second conductivity type, exposed to the other main surface of the semiconductor substrate; a base region having the second conductivity type and connecting both the emitter regions; and a gate region having the first conductivity type, disposed in the base region, wherein the main current flowing between both the emitter regions is controlled by the depletion layer formed in the base region due to the gate bias voltage applied to the gate region with respect to the emitter region having the second conductivity type.
FIG. 1 shows a conventional field controlled thyristor in which the gate region is exposed to the main surface of the semiconductor substrate and provided extending along a cathode region. This type of semiconductor device is disclosed in, for example, D.E. Houston et al, "A FIELD TERMINATED DIODE", IEEE Trans Electron Devices, vol. ED-23, p905 (1976) or Japanese Patent Laid-Open specification No. 50176/77. As shown in FIG. 1, a semiconductor substrate 1 comprises a P.sup.+ anode region 11 exposed to the first main surface 101 of the substrate 1; an n base region 12 adjacent to the P.sup.+ anode 11 and exposed to the second main surface 102 of the substrate 1; n.sup.+ cathode regions 13 formed in the n base region 12, adjacent to the second main surface 102; and p.sup.+ gate regions 14 formed in the n base region 12, adjacent to the second main surface and extending along the n.sup.+ cathode regions 13. An anode electrode 15, cathode electrodes 16 and gate electrodes 17 are formed respectively on those portions of the p.sup.+ anode region, n.sup.+ cathode regions and p.sup.+ gate regions which are exposed in the second main surface 102 of the substrate 1. An SiO.sub.2 film 5 is formed on the remaining exposed portions of the second main surface 102. In this semiconductor device, the n.sup.+ cathode regions 13 and the p.sup.+ gate regions 14 are exposed to the second main surface 102 of the substrate 1, with the n base region 12 interposed therebetween. This configuration makes the space between the adjacent portions of the p.sup.+ gate regions 14 large so that a high gate bias voltage is needed to block the main current. As a result, the forward blocking voltage gain, defined as the voltage between anode and cathode divided by the gate bias voltage required to block the anode-cathode voltage, becomes small and the semiconductor device is therefore unsuitable for switching application. Even if the space between the p.sup.+ regions 14 is narrowed so that the forward blocking voltage gain can be improved, the current rating of the device is decreased since the width of each of the n.sup.+ cathode regions 13 must be accordingly decreased. In some extreme cases, there arises a danger of decreasing the switching power capability or thermally destroying the device since the respective narrow widths of the n.sup.+ cathode regions 13 and the cathode electrodes 16 cause the increase in the current density.